Xilinx FPGA xadc evaluation notes, I hope to help you

Xilinx distributor 7 Series FPGA has a built-in ADC module called xadc. Xadc integrates two ADC modules with the highest sampling rate of 1MHz and 1vpp, which can collect analog signals from FPGA and convert them into digital signals. Xadc can measure the temperature, vccint, vccbram and vccaux voltage inside FPGA without any external input signal. In addition, it can also measure the amplitude of up to 17 channels of external differential input analog signals, including dedicated differential signal input signals VP / N and vauxp / n [XC2V1000-4FG456I]. All signals to be measured pass through two 12bit-1msps ADC modules (ADCs) in xadc_ A and ADC_ B) The conversion results are stored in the status registers. Users can read the data in FPGA through DRP interface, or get these data in the debugging interface of vivado software with JTAG. In addition, the configuration parameters of the ADC are provided by the user. The user can write the parameters into the control registers online in real time, so as to control the working state of the ADC in real time. The user can also fix the parameters after initializing the xadc, instead of real-time configuration. The user only needs to wait for the xadc initialization and read the value in the status register continuously. Figure 1 shows the function module diagram of xadc: xx1

1. Hardware working environment

FPGA：kintex-7。 Power supply: 12V / 4A DC power supply. At most, 32 channels of 2Vpp analog signals and 20 channels of external trigger signals are connected to the board. The data transmission interface includes Gigabit Ethernet interface, high-speed optical fiber interface and low-speed USB serial port. XX2

2.Logic development environment XCZU7EG-1FBVB900I

Vivado2017.4。XCZU7EG-1FBVB900IXilinx is the inventor of the FPGA, programmable SoCs, and now, the ACAP. Our highly-flexible programmable silicon, enabled by a suite of advanced software and tools, drives rapid innovation across a wide span of industries and technologies - from consumer to cars to the cloud. Xilinx delivers the most dynamic processing technology in the industry, enabling rapid innovation with its adaptable, intelligent computing.

3. Introduction of logic block diagram of test engineering for XCZU7EV-1FBVB900E

XCZU7EV-1FBVB900E Since the hardware circuit design did not consider the application requirements of external input analog voltage, this test is aimed at the operating temperature inside FPGA, core voltage vccint, vccbram and auxiliary voltage vccaux. 4. Introduction of implementation method The implementation is to read and write the interface of dynamic reconfiguration port (DRP). After the source language parameters of xadc are determined, only the DRP port needs to be read and written. It is OK. The timing is not complicated. The timing diagram given in the official document ug480 is shown in Figure 4 below. We can control the signal according to the timing.XX3 If we don't even bother to look at the sequence diagram, there are other ways. Its official gives the on-chip temperature measurement, vccint, vccbram, vccaux and 4-way vauxp / n [3:0] code routines. The application routine and simulation test sequence are given on page 83 of ug480, which can be directly copied to our project. The DRP control sequence is very simple. Brother xiaoqingcai will not introduce the sequence of DRP port signal one by one here, so it can be seen more clearly through direct simulation 。 5. Board level test We copy the code provided by the government and modify the configuration parameters to test only the four signals of on-chip temperature measurement,XCZU7EG-1FBVB900E vccint, vccbram and vccaux. We also use the block diagram in Figure 3 to build the project and test the function of temperature and voltage online. As shown in Fig. 5, the sequence diagram of the four signals, vccint, vccbram and vccaux, which are monitored by ILA online, are as follows: EOC is the indication signal for each ADC to complete the signal conversion, and EOS is the indication signal for each 4-channel signal conversion. The time interval of each EOC indication signal is 100 DRP clock cycles, so it can be inferred that the sampling rate of ADC is 1msps. Each time the EOS is raised, it means that the user can read the value of four signals from the status register. Figure 5: overall test sequence diagram of 4-channel signals As shown in Fig. 6, we can see that after continuously writing four daddr addresses, the drdy signal will be pulled up for 4 times. We can take out the data for 4 times each time, so as to complete the temperature measurement on chip, the access of vccint, vccbram and vccaux signals. Figure 6: sequence diagram of 4-channel signal test details It can be more obvious from Fig. 7 that every time the drdy is raised, one signal is read. Pull up 4 times to complete one reading process of 4-channel signals, and then monitor EOS signal. As long as it is pulled up again, the value of these 4-channel signals will be read in the status register again, which will be repeated. Figure 7: access when drdy signal is raised The 4-channel data is sent to the computer through the network interface, and the temperature and voltage of FPGA can be displayed in real time by writing the upper computer software, as shown in Figure 8: the working temperature of FPGA fluctuates around 49 °, vccint is ~ 1V, vccbram is ~ 1V, vccaux is ~ 1.8V, which is consistent with the actual power supply voltage o I'm fpgamall. 

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